1. Field of the Invention
The present invention relates to a contour detecting filter device. More specifically, it relates to a contour detecting filter device for digitally detecting contour signals from composite video signals of the
system including frequency-multiplexed luminance signals and chrominance signals.
2. Description of the Prior Art
Various systems have been proposed in the art for detecting contour signals from video data. In television receivers, for example, contour signals are detected from luminance signals to be added to the original luminance signals, thereby to improve sharpness of pictorial images.
A composite video signal S(t) of the PAL system is composed of a luminance signal Y(t) and a chrominance signal C(t) which is obtained by quadrature phase modulation of two color-difference signals U(t) and V(t) at the chrominance subcarrier frequency f.sub.sc (4.43361875 MHz). Namely, the composite video signal S(t) is expressed as follows: ##EQU1## where the sign for V(t) is changed between "+" and "-" per scanning line.
In such a conventional contour detecting filter of the analog or digital type, for example, the aforementioned luminance signal Y(t) has generally been separated from the composite video signal S(t) so as to obtain a horizontal contour signal through a horizontal contour detecting filter and a vertical contour signal through a vertical contour detecting filter with respect to the separated luminance signal Y(t). Description is now made on the horizontal and vertical contour detecting filters.
FIG. 1 shows an example of a conventional horizontal contour detecting filter of the digital system. Referring to FIG. 1, analog composite video signals are supplied from an input terminal 1 to an A-D conversion circuit 2. The A-D conversion circuit 2 is adapted to convert the analog signals into digital signals, thereby to supply the converted digital signals to a luminance/chrominance signal separation circuit 3 which separates the same into luminance signals and chrominance signals. The luminance signals separated by the luminance/chrominance signal separation circuit 3 are supplied to a horizontal contour detecting filter 5. The horizontal contour detecting filter 5 is formed by a first delay circuit 51, a second delay circuit 52, a coefficient multiplier 53 and an adder 54. Contour signals detected by the horizontal contour detecting filter 5 are outputted at an output terminal 4.
Description is now made on the operation of the horizontal contour detecting filter 5 as shown in FIG. 1. The analog composite video signals received in the input terminal 1 are supplied to the A-D conversion circuit 2. The A-D conversion circuit 2 converts the analog composite video signals into digital composite video signals by sampling signals of a predetermined sampling frequency f.sub.s. The digital composite video signals outputted from the A-D conversion circuit 2 are separated into luminance signals and chrominance signals by the luminance/chrominance signal separation circuit 3. The luminance signals separated by the luminance/chrominance signal separation circuit 3 are supplied to the first delay circuit 51 as well as to the adder 54 of the horizontal contour detecting filter 5. Outputs from the first delay circuit 51 are supplied to the second delay circuit 52 as well as to the coefficient multiplier 53. The coefficient multiplier 53 is adapted to multiply the output signals from the first delay circuit 51 by -2. The delay times of the first and second delay circuits 51 and 52 are set at the inverse number of the aforementioned sampling frequency f.sub.s, to be one sampling period T of digital signal series outputted from the A-D conversion circuit 2.
The adder 54 is adapted to add up the outputs from the luminance/chrominance signal separation circuit 3, the coefficient multiplier 53 and the second delay circuit 52. Therefore, assuming that a luminance signal f(t) outputted from the luminance/chrominance signal separation circuit 3 is f(nT) at a time t =nT, the output from the adder 54 is expressed as follows, as understood from the above description: EQU f(nT)-2f(n-1)T+f[(n-2)T]
This is expressive of the second order differentiation with respect to the horizontal direction of the aforementioned luminance signal f(t) on the screen, whereby detected is the horizontal high-frequency component of the luminance signal, i.e., the horizontal contour signal.
FIG. 2 shows an example of a conventional vertical contour detecting filter of the digital system. Referring to FIG. 2, a vertical contour detecting filter 6 is formed by third and fourth delay circuits 61 and 62, a coefficient multiplier 63 and an adder 64. An A-D conversion circuit 2 and a luminance/chrominance signal separation circuit 3 are identical to those in FIG. 1. Each of the third and fourth delay circuits 61 and 62 is formed to have a delay time of one horizontal scanning interval while the coefficient multiplier 63 multiplies outputs from the third delay circuit 61 by -2 and the adder 64 adds up the outputs from the luminance/chrominance signal separation circuit 3, the coefficient multiplier 63 and the fourth delay circuit 62 similarly to those in FIG. 1. Therefore, as obvious from the above description with reference to FIG. 1, an output from the adder 64 of the vertical contour detecting filter 6 as shown in FIG. 2 is expressed as follows: EQU f(nT)-2f(nT-H)=f(nT-2H)
Thus, performed with respect to the luminance signal outputted from the luminance/chrominance signal separation circuit 3 is the second order differentiation in the vertical direction on the screen, whereby detected is the vertical high-frequency component of the luminance signal, i.e., the vertical contour signal.
FIG. 3 shows a conventional contour detecting filter which is formed by combining the horizontal and vertical contour detecting filters as shown in FIGS. 1 and 2. A contour detecting filter 7 as shown in FIG. 3 is adapted to detect horizontal and vertical contour signals, and first and second delay circuits 72 and 73 are identical in delay time to the first and second delay circuits 51 and 52 as hereinabove described with reference to FIG. 1. Fifth and sixth delay circuits 71 and 74 are in delay times obtained by subtracting the delay times of the first and second delay circuits 72 and 73 from one horizontal scanning interval respectively. Thus, in total, the first and fifth delay circuits 72 and 71 are in a delay time for one horizontal scanning interval H while the second and sixth delay circuits 73 and 74 are also in a delay time for one horizontal scanning interval H in total.
A coefficient multiplier 75 is adapted to multiply its input signals by -4, while an adder 76 is adapted to add up outputs from a luminance/chrominance signal separation circuit 3, the fifth delay circuit 71, the coefficient multiplier 75, the second delay circuit 73 and the sixth delay circuit 74.
In other words, the contour detecting filter 7 consists of a vertical contour detecting filter which is formed by the fifth, first, second and sixth delay circuits 71, 72, 73 and 74, the coefficient multiplier 75 and the adder 76 and a horizontal contour detecting filter which is formed by the first and second delay circuits 72 and 73, the coefficient multiplier 75 and the adder 76, thereby to detect vertical and horizontal contour signals. Further, such structure as shown in FIG. 3 can be considered to perform arithmetic on the second order differentiation in the oblique direction, whereby oblique contour signals can also be detected as hereinafter described in detail.
FIG. 4 is a block diagram showing definite structure of the luminance/chrominance signal separation circuit as shown in FIGS. 1 to 3. As shown in FIG. 4, the luminance/chrominance signal separation circuit 3 is formed by a line memory 30, a vertical high-pass filter 31, a horizontal high-pass filter 32, a delay circuit 33 and a subtractor 34. The line memory 30 includes delay circuits 301 and 302 for delaying signals from an A-D conversion circuit 2 by one horizontal scanning interval H to output the same. The line memory 30 receives the signals from the A-D conversion circuit 2 thereby to generate three types of signals including non-delayed signals, the signals delayed by 1H through the delay circuit 301 and those delayed by 2H through the delay circuits 301 and 302. The vertical high-pass filter 301 receives the signals in the three types of delay times from the line memory 30 to detect high-frequency components in the vertical direction on the screen to supply the same to the horizontal high-pass filter 32. Therefore, the vertical high-pass filter 31 includes a -1/4 multiplier 311 which receives the non-delayed signals from the line memory 30 to multiply the same by -1/4 and output the same, a 1/2 multiplier 312 which receives the 1H delay signals from the line memory 30 to multiply the same by 1/2 and output the same, another -1/4 multiplier 313 which multiplies the 2H delay signals received from the line memory 30 by -1/4 to output the same and an adder 314 which adds up the signals from the -1/4 multipliers 311 and 313 and the 1/2 multipliers 312 to supply the result to the horizontal high-pass filter 32.
The horizontal high-pass filter 32 receives the signals from the vertical high-pass filter 31 to detect horizontal high-frequency components, thereby to separate chrominance signals and supply the same to one input terminal of the subtractor 34. Therefore, the horizontal high-pass filter 32 is formed by a delay circuit 321 which delays the signals from the vertical high-pass filter 31 by 2T, a delay circuit 322 which delays the signals from the vertical high-pass filter 31 further by 2T, a delay circuit 322 which delays the signals from the delay circuit 321 further by 2T, a -1/4 multiplier 323 which multiplies the signals from the vertical high-pass filter 31 by -1/4 to output the same, a 1/2 multiplier 324 which multiplies the signals from the delay circuit 321 by 1/2 to output the same, a -1/4 multiplier 325 which multiplies the signals from the delay circuit 322 by -1/4 to output the same and an adder 326 which adds up the signals received from the -1/4 multipliers 323 and 325 and the 1/2 multiplier 324 to output the result.
With reference to FIG. 4, description is now briefly made on the operation of the luminance/chrominance signal separation circuit 3. Operations of the respective filters 31 and 32 and the line memory 30 are hereinafter described in detail. The output signals from the A-D conversion circuit 2 are sequentially detected by the line memory 30 as three signals having the cycle of one horizontal scanning interval H. The vertical high-pass filter 31 receives the output signals from the line memory 30 to detect the high-frequency components in the vertical direction on the screen. The horizontal high-pass filter 32 which is cascade-connected to the vertical high-pass filter 31 detects the high-frequency components in the direction of the horizontal scanning lines to separate the chrominance signals and supply the same to the subtractor 34.
On the other hand, the output signals from the first stage delay circuit 301 of the line memory 30 are delayed by the delay circuit 33 by a period 2 T, which is twice the sampling period T, to be supplied to the subtractor 34. The subtractor 34 subtracts the output signals of the horizontal high-pass filter 32 from the output signals of the delay circuit 33 thereby to obtain luminance signals, which in turn are outputted to the contour detecting filter.
As hereinabove described, the conventional contour detecting filter device detects the contour signals by utilizing only the luminance signal components. Therefore, the delay circuits required for the luminance/chrominance separation circuit 3 for separating the composite video signals into the luminance signals and the chrominance signals cannot be commonly used with the delay circuits required for the horizontal and vertical contour detecting filters, whereby the components are increased in number with inevitable increase in cost.